1. Field of the Invention
The present invention relates to a receiver for receiving a high-definition signal, and more particularly, to a digital demodulator for a high-definition television (hereinafter, referred to as HDTV) receiver, and a method therefor.
2. Description of the Related Art
Since the advent of the black and white television and the color television, there has been a continuing trend to develop televisions that are more realistic, larger and have better definition. Accordingly, the grand alliance (GA)-HDTV system has been proposed in the U.S. in which a vestigial side band (VSB) modulation method is adopted as a modulation method of the GA-HDTV. Accordingly, as the HDTV transmission standard of the USA is determined as an 8-VSB modulation method, HDTV broadcasts will be realized in the near future.
Meanwhile, the demodulation of an existing GA-HDTV receiver is performed using an analog demodulation method. After analog demodulation of a receiving signal, digital signal processing is performed to restore the original signal.
FIG. 1 is a block diagram of a conventional GA-HDTV receiver using an 8-level VSB modulation method. Referring to FIG. 1, a received radio frequency (RF) signal is output as an intermediate frequency (IF) signal through double-conversion by a double-conversion tuner 102. That is, a synthesizer 104 provides a first local oscillation (LO) frequency to the double-conversion tuner 102 according to channel tuning. A first mixer (not shown) in the double-conversion tuner 102 mixes the received RF signal with the first local oscillation (LO) frequency to thus output a first IF signal of a predetermined frequency (920 MHz), and then constantly adjusts the amplitude of the first IF signal according to an automatic gain control (hereinafter, referred to as AGC) signal which is generated from an AGC generator 138. At this time, channel tuning is controlled by a microprocessor (not shown). The automatic gain-controlled first IF signal is mixed with a second LO frequency, which is controlled by a frequency and phase-locked loop (FPLL) circuit 111, in a second mixer (not shown) of the double-conversion tuner 102 and output as a second IF signal of a desired predetermined frequency (44 MHz).
The double-conversion tuner 102 does not accurately pass only HDTV signals having a 6 MHz band but also passes co-channel signals, since its filtering characteristics are not perfect. The co-channel signals cause interference with signals of a desired channel. Accordingly, in order to solve the above problem, the output of the double-conversion tuner 102 passes through a surface acoustic wave (SAW) filter 106 corresponding to a band pass filter having a bandwidth of exactly 6 MHz.
An IF amplifier 108, for continuously maintaining the level of an input signal of an analog-to-digital (A/D) converter 132, controls the amplitude of the IF signal passed through the SAW filter 106 according to the AGC signal generated from the AGC generator 138.
A multiplier 110 multiplies the IF signal of 6 MHz bandwidth passed through the SAW filter 106 by a sinusoidal wave signal output from a phase shifter 114 which receives a fixed third LO frequency which is generated from a local oscillator 112, thus outputting a signal demodulated into a base band. Here, the first multiplier 110 corresponds to a third mixer, and the fixed third LO frequency is 46.69 MHz corresponding to a pilot frequency.
A first low-pass filter (LPF) 116 removes a second-order harmonic component generated after demodulation and passes only base band signals. The first LPF 116 outputs an I signal on an in-phase axis. Here, when automatic frequency control (AFC) is made during frequency acquisition, an I signal, a Q signal on a quadrature-phase axis and a pilot signal are all used. However, in other data processing blocks of a receiver, only the I signal is used.
That is, an automatic frequency control low pass filter (AFC LPF) 118 outputs beat signals which are generated by a difference in frequency between the output of an internal voltage controlled oscillator (VCO) and input pilot signals. Accordingly, the radio frequency is almost removed by the AFC LPF 118 while only the pilot beat frequency remains.
A limiter 120 outputs "+1" when the output of the AFC LPF 118 is larger than "0," and otherwise, outputs "-1." Thus, the pilot beat signal is limited to a signal .+-.1 having a constant amplitude (.+-.1).
Meanwhile, a second multiplier 122 multiplies the IF signal output from the IF amplifier 108 by the fixed third LO frequency output from the local oscillator 112, thus outputting a signal Q on a quadrature-phase axis.
A second LPF 124 removes a second-order harmonic component from the output of the second multiplier 122 in the same manner as that of the first LPF 116 and passes only the Q signal having a base band. A third multiplier 126 multiplies the output of the limiter 120 by the output of the second LPF 124. Thus, the result of the multiplication drives an automatic phase control low pass filter (APC LPF) 128.
The APC LPF 128 outputs a "direct current (DC)" signal, and drives a VCO 130 according to the DC signal. That is, the DC signal output from the APC LPF 128 is fed back to the double-conversion tuner 102 to reduce the above-described difference in frequency and controls the second LO frequency.
When the frequency is locked by repeating such operations, the limiter 120 outputs either "-1" or "+1." At this time, the third multiplier 126 locks the output of the limiter 120 into the phase of the third fixed LO frequency which is output through the second LPF 124. Through such a control process, phase errors of a carrier frequency in a base band frequency become "0."
Meanwhile, an A/D converter 132 samples the output of the FPLL circuit 111 according to a symbol clock signal restored by a symbol timing restorer 134 and converts it into digital data. The symbol timing restorer 134 generates a symbol clock signal and an operational clock signal of the entire system by predicting a sampling point in time of the analog-to-digital (A/D) converter 132. A synchronous signal detector 136 detects a variety of synchronous signals using the output signal of the A/D converter 132 and outputs a synchronous signal necessary for each portion to an HDTV signal processor 142, and detects a data segment synchronous signal and outputs the result to the AGC generator 138. The AGC generator 138 generates an AGC signal according to the amplitude of the data segment synchronous signal and applies the result to the double conversion tuner 102 and the IF amplifier 108.
A DC remover 140 removes a DC component generated by the nonlinear characteristic of the A/D converter 132. The HDTV signal processor 142 processes the output of the DC remover 142 and restores the result to the original signal.
As described in FIG. 1, the FPLL circuit 111 as an analog demodulator of an HDTV receiver provides an obstacle to the miniaturization of a system. Therefore, if a digital demodulator is realized instead of the analog demodulator, the entire signal processing of a receiver can be digitalized. In this case, it is easy to develop a demodulator using a single ASIC chip, and low cost of receivers and uniform performance thereof can be ensured.
However, since the conventional digital demodulator directly samples an IF signal of 44 MHz, it should use a frequency, being twice or greater than the IF signal frequency (44 MHz), as a sampling frequency. Accordingly, a high-speed A/D converter is required with a result that costs increase.